Integrated circuits (IC) are manufactured by forming discrete semiconductor devices on a surface of a semiconductor substrate, such as a silicon wafer. A multi-level network of interconnect structures is then formed to interconnect the devices. Copper is the material of choice for interconnect structures of advanced IC devices having high circuit density. In addition to superior electrical conductivity, copper is more resistant than aluminum to electromigration, a phenomenon that may destroy a thin film conductive line during IC operation.
An IC device comprises a plurality of interconnect structures that are separated from each other and the substrate by the ILD layers. Such structures are generally fabricated using a dual damascene technique that comprises forming an insulator layer (e.g., ILD layer) into which trenches and openings are etched to pattern the conductive lines and contact holes, or vias. The copper is then used to fill (metallize) the trenches and openings in the IMD layer forming the conductive lines and vias, respectively. During the copper metallization process, an excess amount of copper may be deposited onto the substrate. The excess metal may be removed using a planarization process, e.g., chemical-mechanical polishing (CMP) process. After the planarization process, the interconnect structure is embedded in the ILD layer coplanar with an exposed surface of the layer, such that the next wiring layer may be formed on top of the embedded ILD layer.
In the semiconductor industry, much effort is spent in developing smaller IC devices with ever-increasing operating speeds. To increase the circuit density, a dual damascene technique may be used during fabrication of the IC devices. To increase the operating speed of such a device, the ILD layers are formed using materials having dielectric constants less than about 4.0. Such materials are generally referred to as low-k materials. The low-k materials generally comprise carbon-doped dielectrics, such as organic doped silicon glass (OSG), fluorine doped silicon glass (FSG), organic polymers, and the like.
While performance of the active elements in an IC device generally increases as the size of the IC device decreases, this is not the case for the interconnect structures because the resistance and capacitance of the conductive lines increase as the device size decreases. This relationship between interconnect size and performance is sometimes referred to as the Reverse-Scaling Rule (RSR). Because of RSR, the increase in resistance and capacitance of the conductive lines is becoming a dominant factor in determining circuit performance. As a result, continued reductions in IC device size do not simply lead to improved circuit performance, but may lead to worse performance.
The reverse-scaling rule can be particularly problematic when a new generation of an existing IC device is being developed. The most straightforward way to reduce an existing IC device in size is to simply reduce all the lateral dimensions of the various elements with respect to the previous generation. Because of the reverse-scaling rule, however, this cannot be done for the interconnect structure without sacrificing performance.
Accordingly, it would be desirable to provide a procedure for using the same interconnect architecture used in the previous generation and adapting it for a new, smaller generation of IC devices to thereby avoid the need for designing an entirely new interconnect architecture.